1. Field of Invention
The invention relates to interconnects for a semiconductor wafer using immersion/electroless plating in a dual damascene process.
2. Description of Related Art
In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Thus, semiconductor xe2x80x9cchipsxe2x80x9d having three and four levels of metallization are becoming more prevalent as device geometries shrink to sub-micron levels.
One common metal used for forming metal lines (also referred to as wiring) on a wafer is aluminum. Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is also relatively easy to etch. Aluminum is also used as a material for forming interconnections in vias to connect the different metal layers. However, as the size of via/contact holes is scaled down to a sub-micron region, the step coverage problem appears, which has led to reliability problems when using aluminum to form the interconnection between different wiring layers. The poor step coverage in the sub-micron via/contact holes result in high current density and enhance the electromigration.
One material which has received considerable attention as a replacement material for VLSI interconnect metallizations is copper. Since copper has higher resistance to electromigration and lower resistivity than aluminum, it is a more preferred material for interconnect (plugs and wiring) formation than aluminum. However, one serious disadvantage of using copper metallization is that it is difficult to etch. Thus, where it was relatively easier to etch aluminum after deposition to form wiring lines or plugs (both wiring and plugs are referred to as interconnects), substantial additional cost and time are now required to etch copper.
One typical practice in the art is to fabricate copper plugs and wiring by inlaid (Damascene) structures by employing CMP. Dual Damascene processing eliminates not only the need for metal etch (which is increasingly challenging in aluminum interconnects and nearly impossible with copper), but also the need for dielectric gap fill (another challenging process). This technique involves the creation of interconnect lines by first etching a trench or canal in a planar dielectric layer, and then filling that trench with metal, such as aluminum or copper. In dual damascene processing, a second level is involved where a series of holes (i.e., contacts or vias) are etched and filled in addition to the trench. After filling, the metal and dielectric are planarized by chemical-mechanical polishing (CMP). The challenge associated with copper interconnect is how to deposit a thin layer of material on the trench and via as diffusion barrier to prevent copper diffusion. The trick is to keep the diffusion barrier thin so that it does not negatively impact the resistivity of the plug, while still acting as a good barrier to diffusion. A variety of techniques have been developed to deposit copper, including chemical vapor deposition (CVD), plasma vapor deposition (PVD), sputtering, electroplating, and electroless plating. After copper deposition, a chemical mechanical polishing (CMP) process is used to planarize/polish the metal/dielectric surface.
The invention is directed to a fabrication method of copper interconnects using dual damascene processing. Using silicon or polysilicon to provide an active surface, palladium can be selectively deposited on silicon by immersion plating technique. After palladium deposition (about 1000 xc3x85 thick), either a layer of cobalt phosphorus or alloy cobalt/nickel phosphorus or nickel phosphorus is deposited on the palladium layer using the electroless plating technique. This cobalt phosphorus, cobalt/nickel phosphorus alloy, or nickel phosphorus layer serves as a copper diffusion barrier. The via and trench are filled up with copper by an electroless copper plating method and CMP is used to remove the excess copper and planarize/polish the copper/dielectric surface.
These together with other objects of the invention, along with the various features of novelty which characterize the invention, are pointed out with particularity in the claims annexed to and forming a part of this disclosure. For a better understanding of the invention, its operating advantages and the specific objects obtained by its uses, reference should be made to the accompanying drawings and descriptive matter in which there are illustrated preferred embodiments of the invention.